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dsPIC33F

DS70165E-page 182

Preliminary

2007 Microchip Technology Inc.

15.10.2

OVERRIDE SYNCHRONIZATION

If the OSYNC bit in the PWMCON2 register is set, all

output overrides performed via the OVDCON register

are synchronized to the PWM time base. Synchronous

output overrides occur at the following times:

Edge-Aligned mode – when PTMR is zero

Center-Aligned modes – when PTMR is zero and

the value of PTMR matches PTPER

15.11 PWM Output and Polarity Control

There are three device Configuration bits associated

with the PWM module that provide PWM output pin

control:

HPOL Configuration bit

LPOL Configuration bit

PWMPIN Configuration bit

These three bits in the FPOR Configuration register

(see Section 23.0 “Special Features”) work in con-

junction with the eight PWM Enable bits (PENxH<4:1>,

PENxL<4:1>) located in the PWMCON1 SFR. The

Configuration bits and PWM Enable bits ensure that

the PWM pins are in the correct states after a device

Reset occurs. The PWMPIN configuration fuse allows

the PWM module outputs to be optionally enabled on a

device Reset. If PWMPIN = 0, the PWM outputs will be

driven to their inactive states at Reset. If PWMPIN = 1

(default), the PWM outputs will be tri-stated. The HPOL

bit specifies the polarity for the PWMxH outputs,

whereas the LPOL bit specifies the polarity for the

PWMxL outputs.

15.11.1

OUTPUT PIN CONTROL

The PENxH<4:1> and PENxL<4:1> control bits in the

PWMCON1 SFR enable each high PWM output pin

and each low PWM output pin, respectively. If a partic-

ular PWM output pin is not enabled, it is treated as a

general purpose I/O pin.

15.12 PWM Fault Pins

There are two Fault pins (FLTA and FLTB) associated

with the PWM module. When asserted, these pins can

optionally drive each of the PWM I/O pins to a defined

state.

15.12.1

FAULT PIN ENABLE BITS

The FLTACON and FLTBCON SFRs each have four

control bits that determine whether a particular pair of

PWM I/O pins is to be controlled by the Fault input pin.

To enable a specific PWM I/O pin pair for Fault

overrides, the corresponding bit should be set in the

FLTACON or FLTBCON register.

If all enable bits are cleared in the FLTACON or

FLTBCON register, then the corresponding Fault input

pin has no effect on the PWM module and the pin may

be used as a general purpose interrupt or I/O pin.

15.12.2

FAULT STATES

The FLTACON and FLTBCON Special Function

Registers have eight bits each that determine the state

of each PWM I/O pin when it is overridden by a Fault

input. When these bits are cleared, the PWM I/O pin is

driven to the inactive state. If the bit is set, the PWM

I/O pin will be driven to the active state. The active

and inactive states are referenced to the polarity

defined for each PWM I/O pin (HPOL and LPOL

polarity control bits).

A special case exists when a PWM module I/O pair is

in the Complementary mode and both pins are pro-

grammed to be active on a Fault condition. The

PWMxH pin always has priority in the Complementary

mode so that both I/O pins cannot be driven active

simultaneously.

15.12.3

FAULT PIN PRIORITY

If both Fault input pins have been assigned to control a

particular PWM I/O pin, the Fault state programmed for

the Fault A input pin will take priority over the Fault B

input pin.

Note:

The Fault pin logic can operate indepen-

dent of the PWM logic. If all the enable bits

in the FLTACON/FLTBCON registers are

cleared, then the Fault pin(s) could be

used as general purpose interrupt pin(s).

Each Fault pin has an interrupt vector,

interrupt flag bit and interrupt priority bits

associated with it.

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